MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

READs

READ bursts are initiated with a READ command,

as shown in Figure 5.

The starting column and bank addresses are pro-

vided with the READ command and AUTO

PRECHARGE is either enabled or disabled for that burst

access. If AUTO PRECHARGE is enabled, the row being

accessed is precharged at the completion of the burst.

For the generic READ commands used in the following

illustrations, AUTO PRECHARGE is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available

following the CAS latency after the READ command.

Each subsequent data-out element will be valid by the

next positive clock edge. Figure 6 shows general timing

for each possible CAS latency setting.

16Mb: x16

IT SDRAM

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-

Z. A full-page burst will continue until terminated (at

the end of the page it will wrap to column 0 and

continue).

Data from any READ burst may be truncated with

a subsequent READ command, and data from a fixed-

length READ burst may be immediately followed by

data from a subsequent READ command. In either

case, a continuous flow of data can be maintained. The

first data element from the new burst follows either the

last element of a completed burst, or the last desired

data element of a longer burst which is being trun-

cated. The new READ command should be issued x

cycles before the clock edge at which the last desired

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0-A7

A8-A9

A10

BA

COLUMN

ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK 1

BANK 0

Figure 5

READ Command

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

T0

T1

T2

CLK

COMMAND

DQ

READ

tLZ

tAC

NOP

tOH

DOUT

CAS Latency = 1

T0

T1

T2

T3

CLK

COMMAND

DQ

READ

NOP

tLZ

tAC

CAS Latency = 2

NOP

tOH

DOUT

CLK

COMMAND

T0

READ

DQ

T1

T2

NOP

NOP

tLZ

tAC

CAS Latency = 3

Figure 6

CAS Latency

T3

T4

NOP

tOH

DOUT

DON’T CARE

UNDEFINED

13

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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