MSC8122 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC8122

Quad Digital Signal Processor

Freescale Semiconductor 

Electrical Characteristics

VIH

VDDH + 17%

VDDH + 8%

VDDH

VIL

GND

GND – 0.3 V

GND – 0.7 V

Must not exceed 10% of clock period

Figure 5. Overshoot/Undershoot Voltage for VIH and VIL

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When

systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF

load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down

to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.

When calculating overall loading, also consider additional RC delay.

2.5.1 Output Buffer Impedances

Table 6. Output Buffer Impedances

Output Buffers

Typical Impedance (Ω)

System bus

50

Memory controller

50

Parallel I/O

50

Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

2.5.2 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3

describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the

following guidelines when starting up an MSC8122 device:

• PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.

• If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD

levels and then the VDDH levels (see Figure 7).

• CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET

deassertion to guarantee correct device operation (see Figure 6 and Figure 7).

• CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period.

Note: See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design

recommendations.

The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are

raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

16

Freescale Semiconductor

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