MSC8122 View Datasheet(PDF) - Freescale Semiconductor
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Description
Manufacturer
MSC8122 Datasheet PDF : 48 Pages
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Electrical Characteristics
Table 11 summarizes the reset actions that occur as a result of the different reset sources.
Table 11. Reset Actions for Each Reset Source
Reset Action/Reset Source
Configuration pins sampled (Refer to
Section 2.5.4.1 for details).
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
Power-On
Reset
(PORESET)
External only
Yes
Hard Reset (HRESET)
External or Internal
(Software Watchdog or
Bus Monitor)
No
Soft Reset (SRESET)
External
No
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
No
Yes
No
No
No
Yes
No
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Depends on command
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
VDD and VDDH are both at their nominal levels.
2.5.4.2 Reset Configuration
The MSC8122 has two mechanisms for writing the reset configuration:
• Through the direct slave interface (DSI)
• Through the system bus. When the reset configuration is written through the system bus, the MSC8122 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
• RSTCONF
• CNFGS
• DSISYNC
• DSI64
• CHIP_ID[0–3]
• BM[0–2]
• SWTE
• MODCK[1–2]
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15
20
Freescale Semiconductor
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