MSC8122 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC8122

Quad Digital Signal Processor

Freescale Semiconductor 

Electrical Characteristics

In all cases, the power-up sequence must follow the guidelines shown in Figure 8.

V

3.3 V

B

A

VDDH (IO)

1.2 V

VDD/VCCSYN

Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN

t (time)

The following rules apply:

1. During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.

The duration of interval A should be kept below 10 ms.

2. The duration of timing interval B should be kept as small as possible and less than 10 ms.

2.5.3 Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for

internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum

frequency values are not exceeded.

Table 7. Maximum Frequencies

Characteristic

Core frequency

Reference frequency (REFCLK)

Internal bus frequency (BLCK)

DSI clock frequency (HCLKIN)

• Core frequency = 300 MHz

• Core frequency = 400/500 MHz

External clock frequency (CLKIN or CLKOUT)

Maximum in MHz

300/400/500

100/133/166

100/133/166

HCLKIN ≤ (min{70 MHz, CLKOUT})

HCLKIN ≤ (min{100 MHz, CLKOUT})

100/133/166

Table 8. Clock Frequencies

Characteristics

Symbol

300 MHz Device

Min

Max

CLKIN frequency

FCLKIN

20

100

BCLK frequency

FBCLK

40

100

Reference clock (REFCLK) frequency

FREFCLK

40

100

Output clock (CLKOUT) frequency

FCLKOUT

40

100

SC140 core clock frequency

FCORE

200

300

Note: The rise and fall time of external clocks should be 3 ns maximum

400 MHz Device

Min

Max

20

133.3

40

133.3

40

133.3

40

133.3

200

400

500 MHz Device

Min

Max

20

166.7

40

166.7

40

166.7

40

166.7

200

500

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

18

Freescale Semiconductor

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