NT5CB128M8DN View Datasheet(PDF) - Nanya Technology
Part Name
Description
Manufacturer
NT5CB128M8DN Datasheet PDF : 138 Pages
| |||
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Electrical Characteristics & AC Timing
Table 63: Timing Parameter by Speed Bin (DDR3/L-1600, 1866, 2133Mbps)
DDR3/L-1600 DDR3-1866 DDR3-2133
Parameter
Symbol
Min. Max. Min. Max. Min. Max.
N
Units o
t
e
Minimum Clock Cycle Time (DLL off
mode)
Average Clock Period
Average high pulse width
Average low pulse width
tCK
(DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
Absolute Clock Period
tCK(abs)
Absolute clock HIGH pulse width
tCH(abs)
Absolute clock LOW pulse width
tCL(abs)
Clock Period Jitter
JIT(per)
Clock Period Jitter during DLL locking
period
JIT(per, lck)
Cycle to Cycle Period Jitter
tJIT(cc)
Cycle to Cycle Period Jitter during DLL
locking period
JIT(cc, lck)
Duty Cycle Jitter
tJIT(duty)
Cumulative error across 2 cycles
tERR(2per)
Cumulative error across 3 cycles
tERR(3per)
Cumulative error across 4 cycles
tERR(4per)
Cumulative error across 5 cycles
tERR(5per)
Cumulative error across 6 cycles
tERR(6per)
Cumulative error across 7 cycles
tERR(7per)
Cumulative error across 8 cycles
tERR(8per)
Cumulative error across 9 cycles
tERR(9per)
Cumulative error across 10 cycles
tERR(10per)
Cumulative error across 11 cycles
tERR(11per)
Cumulative error across 12 cycles
tERR(12per)
Cumulative
50 cycles
error
across
n
=
13,
14
.
.
.
49,
tERR(nper)
Data Timing
DQS, DQS# to DQ skew, per group, per
access
tDQSQ
DQ output hold time from DQS, DQS# tQH
DQ low-impedance time from CK, CK# tLZ(DQ)
DQ high impedance time from CK, CK# tHZ(DQ)
Data setup time to DQS, DQS#
tDS(base)
referenced to Vih(ac) / Vil(ac) levels
AC175/160
Data setup time to DQS, DQS#
tDS(base)
referenced to Vih(ac) / Vil(ac) levels
AC150/135
Data hold time from DQS, DQS#
tDH(base)
referenced to Vih(dc) / Vil(dc) levels
DC100/90
DQ and DM Input pulse width for each
input
tDIPW
Data Strobe Timing
DQS,DQS# differential READ Preamble tRPRE
DQS, DQS# differential READ Postamble tRPST
DQS, DQS# differential output high time tQSH
DQS, DQS# differential output low time tQSL
DQS, DQS# differential WRITE Preamble tWPRE
DQS, DQS# differential WRITE
Postamble
tWPST
DQS, DQS# rising edge output access
time from rising CK, CK#
tDQSCK
DQS and DQS# low-impedance time tLZ(DQS)
8
-
8
-
8
-
Refer to "Standard Speed Bins)
0.47
0.53 0.47 0.53 0.47 0.53
0.47
0.53 0.47 0.53 0.47 0.53
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
0.43
-
0.43 -
0.43 -
0.43
-
0.43 -
0.43 -
-70
70
-60 60
-50 50
-60
60
-50 50
-40 40
140
120
100
120
100
80
-
-
-
-
-
-
-103
103 -88 88
-74 74
-122
122 -105 105 -87 87
-136
136 -117 117 -97 97
-147
147 -126 126 -105 105
-155
155 -133 133 -111 111
-163
163 -139 139 -116 116
-169
169 -145 145 -121 121
-175
175 -150 150 -125 125
-180
180 -154 154 -128 128
-184
184 -158 158 -132 132
-188
188 -161 161 -134 134
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max
ns
ʳ
ps
ʳ
tCK(avg) ʳ
tCK(avg) ʳ
ps
ʳ
tCK(avg) ʳ
tCK(avg) ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
-
0.38
-450
-
100 -
85
-
0.38 -
225 -390 195
225 -
195
See Table.70 on page 132
360
-
320 ʳ -
-
75
0.38 -
-360 180
-
180
280 -
ps
ʳ
tCK(avg) ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
0.9
0.3
0.4
0.4
0.9
0.3
-225
-450
Note 19 0.9
Note 11 0.3
-
0.4
-
0.4
-
0.9
-
0.3
Note 19 0.9
Note 11 0.3
-
0.4
-
0.4
-
0.9
-
0.3
Note 19 tCK(avg) ʳ
Note 11 tCK(avg) ʳ
-
tCK(avg) ʳ
-
tCK(avg) ʳ
-
tCK(avg) ʳ
-
tCK(avg) ʳ
225 -195 195 -180 180 tCK(avg) ʳ
225 -390 195 -360 180 tCK(avg) ʳ
REV 1.2
May. 2011
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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