NT5CB128M8DN View Datasheet(PDF) - Nanya Technology
Part Name
Description
Manufacturer
NT5CB128M8DN Datasheet PDF : 138 Pages
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NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
DQS, DQS# differential input low pulse
width
tDQSL
DQS, DQS# differential input high pulse
width
tDQSH
DQS,
edge
DQS#
rising
edge
to
CK,
CK#
rising
tDQSS
DQS, DQS# falling edge setup time to
CK, CK# rising edge
tDSS
DQS, DQS# falling edge hold time from
CK, CK# rising edge
tDSH
Command and Address Timing
DLL locking time
tDLLK
Internal READ Command to
PRECHARGE Command delay
tRTP
Delay from start of internal write
transaction to internal read command
tWTR
WRITE recovery time
tWR
Mode Register Set command cycle time tMRD
Mode Register Set command update
delay
tMOD
ACT to internal read or write delay time tRCD
PRE command period
tRP
ACT to ACT or REF command period tRC
CAS# to CAS# command delay
tCCD
Auto precharge write recovery +
precharge time
tDAL(min)
Multi-Purpose Register Recovery Time tMPRR
ACTIVE to PRECHARGE command
period
tRAS
ACTIVE to ACTIVE command period for
1KB page size
tRRD
ACTIVE to ACTIVE command period for
2KB page size
tRRD
Four activate window for 1KB page size tFAW
Four activate window for 2KB page size tFAW
Command
CK#
referenced
and Address setup
to Vih(ac) / Vil(ac)
time to
levels
CK,
tIS(base)
AC175/160
Command
CK#
referenced
and Address setup
to Vih(ac) / Vil(ac)
time to
levels
CK,
tIH(base)
AC150/135
Command and Address hold time from
CK, CK#
referenced to Vih(dc) / Vil(dc) levels
tIS(base)
DC100/90
Control and
each input
Address
Input
pulse
width
for
tIPW
Calibration Timing
Power-up and RESET calibration time tZQinit
Normal operation Full calibration time tZQoper
Normal operation Short calibration time tZQCS
Reset Timing
Exit Reset from CKE HIGH to a valid
command
tXPR
Self Refresh Timings
Exit Self Refresh to commands not
requiring a locked DLL
tXS
Exit Self Refresh to commands requiring
a locked DLL
tXSDLL
Minimum CKE low width for Self Refresh tCKESR
-
0.45
0.45
-0.27
0.18
0.18
225 -
195 -
180
0.55 0.45 0.55 0.45 0.55
0.55 0.45 0.55 0.45 0.55
0.27 -0.27 0.27 -0.27 0.27
-
0.18 -
0.18 -
-
0.18 -
0.18 -
512
-
512 -
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.: -
15
-
15 -
4
-
4
-
tMODmin.: max(12nCK, 15ns)
tMODmax.:
ʳ
ʳʳ See Table.1 on page 1
4
-
4
-
WR + roundup(tRP / tCK(avg))
1
-
1
-
Standard Speed Bins
tRRDmin.: max(4nCK, 6ns)
tRRDmax.:
tRRDmin.: max(4nCK, 7.5ns)
tRRDmax.:
30
0
27 -
40
0
35 -
512 -
15 -
4
-
4
-
1
-
25 -
35 -
See Table.64 on page129
560
-
535 -
470 -
512
-
256
-
64
-
512 -
256 -
64 -
512 -
256 -
64 -
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
tXPRmax.: -
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tXSmax.: -
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
tCKESRmin.: tCKE(min) + 1 nCK
tCK(avg) ʳ
tCK(avg) ʳ
tCK(avg) ʳ
tCK(avg) ʳ
tCK(avg) ʳ
tCK(avg) ʳ
nCK ʳ
ʳ
ʳ
ʳ
ʳ
ns
ʳ
nCK ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
nCK ʳ
nCK ʳ
nCK ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ns
ʳ
ns
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
ps
ʳ
nCK ʳ
nCK ʳ
nCK ʳ
ʳ
ʳ
ʳ
ʳ
nCK ʳ
ʳ
ʳ
REV 1.2
May. 2011
CONSUMER DRAM
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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