NT5CB128M8DN View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT5CB128M8DN

1Gb DDR3 D-die SDRAM

Nanya Technology 

NT5CB128M8DN/NT5CB64M16DP

NT5CC128M8DN/NT5CC64M16DP

1Gb DDR3 D-die SDRAM

Address / Command Setup, Hold, and Derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)

and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.

Example: tIS (total setup time) = tIS(base) + delta tIS

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first

crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line

between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal

from the ac level to dc level is used for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line

between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the

nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal

from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain

above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid

input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to

complete the transition and reach VIH/IL(ac).

REV 1.2

May. 2011

CONSUMER DRAM

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