S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Table 61. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)
CFI Parameter
Relative Byte
Address Offset
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
SFDP Parameter
Relative Byte
Address Offset
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
SFDP Dword Name
JEDEC Basic Flash
Parameter Dword-2
JEDEC Basic Flash
Parameter Dword-3
JEDEC Basic Flash
Parameter Dword-4
0Fh
10h
JEDEC Basic Flash
11h
Parameter Dword-5
12h
13h
14h
15h
JEDEC Basic Flash
16h
Parameter Dword-6
17h
18h
19h
JEDEC Basic Flash
1Ah
Parameter Dword-7
1Bh
1Ch
1Dh
JEDEC Basic Flash
1Eh
Parameter Dword-8
1Fh
20h
21h
JEDEC Basic Flash
22h
Parameter Dword-9
23h
Data
Description
FFh Density in bits, zero based, 128Mb = 07FFFFFFh
FFh
FFh
07h
44h
Bits 7:5 = number of Quad I/O Mode cycles = 010b
Bits 4:0 = number of Quad I/O Dummy cycles = 00100b for default latency code 00b
EBh Quad I/O instruction code
08h
Bits 23:21 = number of Quad Out Mode cycles = 000b
Bits 20:16 = number of Quad Out Dummy cycles = 01000b
6Bh Quad Out instruction code
08h
Bits 7:5 = number of Dual Out Mode cycles = 000b
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
3Bh Dual Out instruction code
Bits 23:21 = number of Dual I/O Mode cycles
80h 20:16 = number of Dual I/O Dummy cycles
Default Latency code = 00b
BBh Dual I/O instruction code
Bits 7:5 RFU = 111b
EEh
Bit 4 = Quad All not supported = 0b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
FFh Bits 15:8 = RFU = FFh
FFh Bits 23:16 = RFU = FFh
FFh Bits 31:24 = RFU = FFh
FFh Bits 7:0 = RFU = FFh
FFh Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
FFh Dual All instruction code
FFh Bits 7:0 = RFU = FFh
FFh Bits 15:8 = RFU = FFh
FFh
Bits 23:21 = number of Quad All Mode cycles = 111b
Bits 20:16 = number of Quad All Dummy cycles = 11111b
FFh Quad All instruction code
0Ch Erase type 1 size 2N Bytes = 4KB = 0Ch (for Hybrid Sector Initial Delivery State)
20h Erase type 1 instruction
10h Erase type 2 size 2N Bytes = 64KB = 10h (for Hybrid Sector Initial Delivery State)
D8h Erase type 2 instruction
12h Erase type 3 size 2N Bytes = 256KB = 12h (if Uniform Sectors enabled)
D8h Erase type 3 instruction
00h Erase type 4 size 2N Bytes = not supported = 00h
FFh Erase type 4 instruction = not supported = FFh
Document Number: 001-98282 Rev. *I
Page 127 of 142
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