S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Table 61. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)
CFI Parameter
Relative Byte
Address Offset
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
SFDP Parameter
Relative Byte
Address Offset
3Ch
3Dh
3Eh
SFDP Dword Name
JEDEC Basic Flash
Parameter Dword-16
3Fh
40h
41h
42h
JEDEC Sector Map
Parameter Dword-1
Config. Detect-1
43h
44h
45h
JEDEC Sector Map
Parameter Dword-2
46h
Config. Detect-1
47h
48h
49h
4Ah
JEDEC Sector Map
Parameter Dword-3
Config. Detect-2
4Bh
4Ch
4Dh
JEDEC Sector Map
Parameter Dword-4
4Eh
Config. Detect-2
4Fh
Data
Description
F0h Bits 31:24 = Enter 4-Byte Addressing
= xxxx_1xxxb: 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is
28h used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte address
FAh
mode is active and A[30:24] bits are don’t care. Read with instruction 16h. Write
instruction is 17h with 1 byte of data. When MSB is cleared to ‘0’, select the active 128
Mbit segment by setting the appropriate A[30:24] bits and use 3-Byte addressing.
+ xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data
sheet for the instruction set definition or look for 4 Byte Address Parameter Table.
+ 1xxx_xxxxb: Reserved
= 10101000b
Bits 23:14 = Exit 4-Byte Addressing
= xx_xxxx_1xxxb: 8-bit volatile bank register used to define A[30:A24] bits. MSB
(bit[7]) is used to enable/disable 4-byte address mode. When MSB is cleared to ‘0’,
3-byte address mode is active and A30:A24 are used to select the active 128 Mbit
memory segment. Read with instruction 16h. Write instruction is 17h, data length is 1
byte.
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved = 1111101000b
A8h Bits 13:8 = Soft Reset and Rescue Sequence Support
= x0_1xxxb: issue instruction F0h
+ 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the
device may be operating in this mode. = 101000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status
Register 1
= xx1_xxxxb: Status Register 1 contains a mix of volatile and non-volatile bits. The 06h
instruction is used to enable writing of the register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1110000b
Binary Fields: 10101000-1111101000-101000-1-1110000
Nibble Format: 1010_1000_1111_1010_0010_1000_1111_0000
Hex Format: A8_FA_28_F0
FCh Bits 31:24 = Read data mask = 10000000b: Select bit 7 of the data byte for D8h_O
value
07h Bits 23:22 = Configuration detection command address length = 00b: No address
30h
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 0000b: zero latency
Bits 15:8 = Configuration detection instruction = 07h: Read status register 2
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
80h Bit 0 = not the end descriptor = 0
Binary Fields: 10000000-00-11-0000-00000111-111111-0-0
Nibble Format: 1000_0000_0011_0000_0000_0111_1111_1100
Hex Format: 80_30_07_FC
FFh
FFh Bits 31:0 = Sector map configuration detection command address = FFFFh: no
FFh address
FFh
FDh Bits 31:24 = Read data mask = 00000100b: Select bit 2 of the data byte for TBPARM
value
35h Bits 23:22 = Configuration detection command address length = 00b: No address
30h
Bits 21:20 = RFU = 11b
Bits 19:16 = Configuration detection command latency = 0000b: zero latency
Bits 15:8 = Configuration detection instruction = 35h: Read configuration register 1
Bits 7:2 = RFU = 111111b
Bit 1 = Command Descriptor = 0
04h Bit 0 = The end descriptor = 1
Binary Fields: 00000100-00-11-0000-00110101-111111-0-1
Nibble Format: 0000_0100_0011_0000_0011_0101_1111_1101
Hex Format: 04_30_35_FD
FFh
FFh Bits 31:0 = Sector map configuration detection command address = FFFFh: no
FFh address
FFh
Document Number: 001-98282 Rev. *I
Page 130 of 142
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