S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Table 61. CFI Alternate Vendor-Specific Extended Query Parameter A5h, JEDEC SFDP Rev B (Continued)
CFI Parameter
Relative Byte
Address Offset
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
SFDP Parameter
Relative Byte
Address Offset
34h
35h
36h
SFDP Dword Name
JEDEC Basic Flash
Parameter Dword-14
37h
38h
39h
3Ah
JEDEC Basic Flash
Parameter Dword-15
3Bh
Data
Description
F7h Bit 31 = Deep Power Down Supported = not supported = 1
Bits 30:23 = Enter Deep Power Down Instruction = not supported = FFh
FFh Bits 22:15 = Exit Deep Power Down Instruction = not supported = FFh
FFh
Bits 14:13 = Exit Deep Power Down to next operation delay units = (00b: 128ns, 01b:
1us, 10b: 8us, 11b: 64us) = 64us = 11b
Bits 12:8 = Exit Deep Power Down to next operation delay count = 11111b, Exit Deep
Power Down to next operation delay = (count+1)*units = not supported
Bits 7:4 = RFU = Fh
Bit 3:2 = Status Register Polling Device Busy
= 01b: Legacy status polling supported = Use legacy polling by reading the Status
FFh
Register with 05h instruction and checking WIP bit[0] (0=ready; 1=busy).
Bits 1:0 = RFU = 11b
Binary Fields: 1-11111111-11111111-11-11111-1111-01-11
Nibble Format: 1111_1111_1111_1111_1111_1111_1111_0111
Hex Format: FF_FF_FF_F7
00h Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = not supported = 0b
F6h Bits 22:20 = Quad Enable Requirements
5Dh
= 101b: QE is bit 1 of the status register 2 (SFDP spec calls this Status Register 2,
FL127S calls this Configuration Register 1). Status register 1 is read using Read
Status instruction 05h. Status register 2 (FL127S Configuration Register 1) is read
using instruction 35h. QE is set via Write Status instruction 01h with two data bytes
where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes
where bit 1 of the second byte is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bits[7:0] = Axh
+ 1xxxb: RFU
= 1101b
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current
read operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the
FFh
mode prior to the next read operation.
+ x1_xxxxb: Mode Bit[7:0] != Axh
+ 1x_x1xx: RFU
= 11_1101
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences
= 0_0000b: 4-4-4 not supported
= 00000b
Bits 3:0 = 4-4-4 mode disable sequences
= 0000b: 4-4-4 not supported
= 0000b
Binary Fields: 11111111-0-101-1101-111101-1-00000-0000
Nibble Format: 1111_1111_0101_1101_1111_0110_0000_0000
Hex Format: FF_5D_F6_00
Document Number: 001-98282 Rev. *I
Page 129 of 142
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