S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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Description
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host
driving the Chip Select (CS#) signal low throughout a command.
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an eight bit (byte) instruction. The instruction is always presented only as a single bit serial
sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising edge. The
instruction selects the type of information transfer or device operation to be performed.
The instruction may be stand alone or may be followed by address bits to select a byte location within one of several
address spaces in the device. The instruction determines the address space used. The address may be either a 24-bit or a
32-bit address. The address transfers occur on SCK rising edge.
The width of all transfers following the instruction are determined by the instruction sent. Following transfers may continue
to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per (dual) transfer on
the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on the IO0-IO3 signals. Within the dual or
quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher
numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
Some instructions send an instruction modifier called mode bits, following the address, to indicate that the next command
will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an
instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period
before read data is returned to the host.
Write data bit transfers occur on SCK rising edge.
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also
referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on
SCK falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the host on
the following SCK rising edge. Each following transfer occurs on the next SCK rising edge.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS#
signal high. The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the
command.
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after
the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be
driven high when the number of clock cycles after CS# signal was driven low is an exact multiple of eight cycles. If the CS#
signal does not go high exactly at the eight SCK cycle boundary of the instruction or write data, the command is rejected
and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The data bits are
shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address byte sent first.
Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored.
The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during
an embedded operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing
command is available to determine when the command completes execution and whether the command was successful.
Document Number: 001-98282 Rev. *I
Page 16 of 142
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