S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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Description
Manufacturer
S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Table 5. Interface States Summary with HOLD# / IO3 Enabled
Interface State
Power-Off
Low Power Hardware Data
Protection
Power-On (Cold) Reset
Interface Standby
Instruction Cycle (Legacy SPI)
Hold Cycle
Single Input Cycle
Host to Memory Transfer
Single Latency (Dummy) Cycle
Single Output Cycle Memory to
Host Transfer
Dual Input Cycle Host to Memory
Transfer
Dual Latency (Dummy) Cycle
Dual Output Cycle Memory to Host
Transfer
QPP Address Input Cycle Host to
Memory Transfer
Quad Input Cycle Host to Memory
Transfer
Quad Latency (Dummy) Cycle
Quad Output Cycle Memory to
Host Transfer
VDD
<VCC (low)
<VCC (cut-off)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
SCK
X
X
X
X
HT
HV or HT
HT
HT
HT
HT
HT
HT
HT
HT
HT
HT
Legend
Z = no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
X = HL or HH or Z
HT = toggling between HL and HH
ML = Memory driving VIL
MH = Memory driving VIH
MV = either ML or MH
CS#
X
X
HH
HH
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HOLD# /
IO3
X
X
X
X
HH
HL
HH
HH
HH
WP# /
IO2
X
X
X
X
HV
X
X
X
X
SO /
IO1
Z
Z
Z
Z
Z
X
Z
Z
MV
SI / IO0
X
X
X
X
HV
X
HV
X
X
HH
X
HV
HV
HH
X
X
X
HH
X
MV
MV
X
X
X
HV
HV
HV
HV
HV
X
X
X
X
MV
MV
MV
MV
3.3.1
Power-Off
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not
react to external signals, and is prevented from performing any program or erase operation.
3.3.2
Low Power Hardware Data Protection
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not
start when the core supply voltage is out of the operating range.
Document Number: 001-98282 Rev. *I
Page 21 of 142
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