S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
3.3 Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3. Interface States Summary with Separate Reset
Interface State
Power-Off
Low Power Hardware Data
Protection
Power-On (Cold) Reset
Hardware (Warm) Reset
Interface Standby
Instruction Cycle
Hold Cycle
Single Input Cycle Host to
Memory Transfer
Single Latency (Dummy) Cycle
Single Output Cycle Memory to
Host Transfer
Dual Input Cycle Host to
Memory Transfer
Dual Latency (Dummy) Cycle
Dual Output Cycle Memory to
Host Transfer
QPP Address Input Cycle Host
to Memory Transfer
Quad Input Cycle Host to
Memory Transfer
Quad Latency (Dummy) Cycle
Quad Output Cycle Memory to
Host Transfer
VCC
<VCC (low)
<VCC (cut-off)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
RESET#
X
X
X
HL
HH
HH
HH
HH
HH
HH
SCK
X
X
X
X
X
HT
HV or HT
HT
HT
HT
CS#
HOLD# /
IO3
X
X
X
X
HH
X
X
X
HH
X
HL
HH
HL
HL
HL
HH
HL
HH
HL
HH
HH
HT
HL
HH
HH
HT
HL
HH
HH
HT
HL
HH
HH
HT
HL
X
HH
HT
HL
HV
HH
HT
HL
X
HH
HT
HL
MV
WP# /
IO2
X
X
X
X
X
HV
X
X
X
X
X
X
X
X
HV
X
MV
SO /
IO1
Z
SI / IO0
X
Z
X
Z
X
Z
X
Z
X
Z
HV
X
X
Z
HV
Z
X
MV
X
HV
HV
X
X
MV MV
X
HV
HV
HV
X
X
MV MV
Legend
Z = no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
X = HL or HH or Z
HT = toggling between HL and HH
ML = Memory driving VIL
MH = Memory driving VIH
MV = either ML or MH
Document Number: 001-98282 Rev. *I
Page 19 of 142
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