S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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Description
Manufacturer
S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
Table 4. Interface States Summary with IO3 / RESET# Enabled
Interface State
Power-Off
Low Power Hardware Data
Protection
Power-On (Cold) Reset
Hardware (Warm) Reset —
Non-Quad Mode
Hardware (Warm) Reset — Quad
Mode
Interface Standby
Instruction Cycle (Legacy SPI)
Single Input Cycle
Host to Memory Transfer
Single Latency (Dummy) Cycle
Single Output Cycle Memory to
Host Transfer
Dual Input Cycle Host to Memory
Transfer
Dual Latency (Dummy) Cycle
Dual Output Cycle Memory to Host
Transfer
QPP Address Input Cycle Host to
Memory Transfer
Quad Input Cycle Host to Memory
Transfer
Quad Latency (Dummy) Cycle
Quad Output Cycle Memory to
Host Transfer
VCC
<VCC (low)
<VCC (cut-off)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
≥VCC (min)
SCK
X
X
X
X
X
X
HT
HT
HT
HT
HT
HT
HT
HT
HT
HT
HT
Legend
Z = no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
X = HL or HH or Z
HT = toggling between HL and HH
ML = Memory driving VIL
MH = Memory driving VIH
MV = either ML or MH
CS#
HOLD# / WP# /
IO3
IO2
SO /
IO1
SI / IO0
X
X
X
Z
X
X
X
X
Z
X
HH
X
X
Z
X
X
HL
X
Z
X
HH
HL
HH
X
HL
HH
HL
HH
HL
HH
HL
HH
X
Z
X
X
Z
X
HV
Z
HV
X
Z
HV
X
Z
X
X
MV
X
HL
HH
HL
HH
HL
HH
X
HV
HV
X
X
X
X
MV
MV
HL
X
X
X
HV
HL
HV
HV
HV
HV
HL
X
X
X
X
HL
MV
MV
MV
MV
Document Number: 001-98282 Rev. *I
Page 20 of 142
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