S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

3.4 Configuration Register Effects on the Interface

The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the

number of mode bit and latency cycles for each type of instruction.

The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and allow Quad Page

Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad I/O

commands.

3.5 Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These

are described below. Other software managed protection methods are discussed in the software section (page 45) of this document.

3.5.1

Power-Up

When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue

to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface

Standby state.

3.5.2

Low Power

When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.5.3

Clock Pulse Count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count that is a multiple of

eight before executing them. A command not having a multiple of 8 clock pulse count is ignored and no error status is set for the

command.

Document Number: 001-98283 Rev. *I

Page 24 of 144

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