S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

5.2.1

Capacitance Characteristics

Table 5.2 Capacitance

Parameter

CIN

COUT

Input Capacitance (applies to SCK, CS#, RESET#)

Output Capacitance (applies to All I/O)

Note:

1. For more information on capacitance, please consult the IBIS models.

5.3 Reset

Test Conditions

1 MHz

1 MHz

Min

Max

Unit

8

pF

8

pF

5.3.1

Power-On (Cold) Reset

The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the moment that VCC rises above

the minimum VCC threshold. See Figure 4.3 on page 27, Table 4.2 on page 27, and Table 5.3 on page 31. The device must not be

selected (CS# to go high with VIO) during power-up (tPU), i.e. no commands may be sent to the device until the end of tPU. RESET#

is ignored during POR. If RESET# is low during POR and remains low through and beyond the end of tPU, CS# must remain high

until tRH after RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a hardware reset.

VCC

VIO

RESET#

CS#

Figure 5.4 Reset Low at the End of POR

tPU

If RESET# is low at tPU end

tRH

CS# must be high at tPU end

VCC

VIO

RESET#

CS#

Figure 5.5 Reset High at the End of POR

tPU

If RESET# is high at tPU end

tPU

CS# may stay high or go low at tPU end

Figure 5.6 POR followed by Hardware Reset

VCC

VIO

RESET#

CS#

tPU

tRS

tPU

Document Number: 001-98283 Rev. *I

Page 30 of 144

Share Link: