MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

recently registered READ or WRITE command prior to

the BURST TERMINATE command will be truncated

as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation

of the SDRAM and is analogous to CAS#-BEFORE-

RAS# (CBR) REFRESH in conventional DRAMs. This

command is nonpersistent, so it must be issued each

time a refresh

is required.

The addressing during an AUTO REFRESH com-

mand is generated by an internal refresh controller.

This means that the address lines are not used to

generate the refresh address, and are “Don’t Care”.

The 1 Meg x 16 SDRAM requires 2,048 AUTO

REFRESH cycles every 64ms (tREF) to ensure that each

row is refreshed. Distributed refresh would be achieved

by providing an AUTO REFRESH command once ev-

ery 31.25µs. Burst refresh could be accomplished by

issuing 2,048 AUTO REFRESH commands consecu-

tively at the minimum cycle rate of tRC.

To provide a 4K refresh scheme, the refresh rate

would be doubled. Thus, 2,048 AUTO-REFRESH com-

mands distributed every 15.625µs would allow the 1

Meg x 16 SDRAM to have a 4K refresh if required. Of

the three types of refreshs options, utilizing the 2,048

cycles every 64ms (31.25µs per refresh) provides the

maximum power savings.

16Mb: x16

IT SDRAM

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the

SDRAM retains data without external clocking. The

SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW).

Once the SELF REFRESH command is registered, all the

inputs to the SDRAM become “Don’t Care,” with the

exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM

provides its own internal clocking, causing it to per-

form its own auto refresh cycles. The SDRAM must

remain in self refresh mode for a minimum period

equal to tRAS, and may remain in self refresh mode for

an indefinite period beyond that.

The procedure for exiting self refresh requires a

sequence of commands. First, CLK must be stable (stable

clock is defined as a signal cycling within timing con-

straints specified for the clock pin) prior to CKE going

back HIGH. Once CKE is HIGH, the SDRAM must have

NOP commands issued (a minimum of two clocks) for

tXSR, because time is required for the completion of

any internal refresh in progress.

Upon exiting self refresh mode, AUTO REFRESH

commands may be issued every 15.625µs or less as both

SELF REFRESH and AUTO REFRESH utilize the row

refresh counter.

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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