DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

7 Electrical Characteristics and Requirements (continued)

7.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs

The DSP16410C does not include any internal circuitry to maintain valid logic levels on input pins or on bidirec-

tional pins that are not driven. For correct device operation and low static power dissipation, valid CMOS levels

must be applied to all input and bidirectional pins. Failure to ensure full CMOS levels (VIL or VIH) on pins that are

not driven (including floating data busses) may result in high static power consumption and possible device failure.

Any unused input pin must be pulled up to the I/O pin supply (VDD2) or pulled down to VSS according to the func-

tional requirements of the pin. The pin can be pulled up or down directly or through a 10 kΩ resistor.

Any unused bidirectional pin statically configured as an input should be pulled to VDD2 or VSS through a 10 kΩ

resistor. Any bidirectional pin that is dynamically configured, such as the SEMI or PIU data busses, should be tied

to VDD2 or VSS through a pull-up/down resistor that supports the performance of the circuit. The value of the resis-

tor should be selected to avoid exceeding the dc voltage and current characteristics of any device attached to the

pin.

If the SEMI interface is unused in the system, the EYMODE pin should be connected to VDD2 to force the internal

data bus transceivers to always be in the output mode. This avoids the need to add 32 pull-up resistors to ED[31:0].

If the SEMI interface is used in the system, the EYMODE pin must be connected to VSS and pull-up or pull-down

resistors must be added to ED[31:0] as described below.

The value of the pull-up resistors used on the SEMI data bus depends on the programmed bus width, 32-bit or

16-bit, as determined by the ESIZE pin. It is recommended that any 16-bit peripheral that is connected to the exter-

nal memory interface of the DSP16410C use the upper 16 bits of the data bus (ED[31:16]). This is required if the

external memory interface is configured as a 16-bit interface. For the following configurations, 10 kΩ pull-up or pull-

down resistors can be used on the external data bus:

s 32-bit SEMI with no 16-bit peripherals

s 32-bit SEMI with 16-bit peripherals connected to ED[31:16]

s 16-bit interface (ED[31:16] only)

If the DSP16410C’s external memory interface is configured for 32-bit operation with 16-bit peripherals on the

lower half of the external data bus (ED[15:0]), the external data bus (ED[31:0]) should have 2 kΩ pull-up or pull-

down resistors to meet the rise or fall time requirements of the DSP16410C*.

The different requirements for the size of the pull-up/pull-down resistors arise from the manner in which SEMI

treats 16-bit accesses if the interface is configured for 32-bit operation. If configured as a 32-bit interface and a

16-bit read is performed to a device on the upper half of the data bus, the SEMI latches the value on the upper

16 bits internally onto the lower 16 bits. This ensures that the lower half of the data bus sees valid logic levels both

in this case and also if the bus is operated as a 16-bit bus. However, if a 16-bit read operation is performed (on a

32-bit bus) to a 16-bit peripheral on the lower 16 bits, no data is latched onto the upper 16 bits, resulting in the

upper half of the bus floating. In this case the smaller pull-up resistors ensure the floating data bits transition to a

valid logic level fast enough to avoid metastability problems when the inputs are latched by the SEMI.

* The 2 kΩ resistor value assumes a bus loading of 30 pF and also ensures IOL is not violated.

Agere Systems Inc.

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