DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation
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Description
Manufacturer
DSP16410C Datasheet PDF : 373 Pages
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DSP16410C Digital Signal Processor
Data Addendum
May 2001
7 Electrical Characteristics and Requirements (continued)
7.3 Power Dissipation (continued)
7.3.2 I/O Power Dissipation
I/O power dissipation is highly dependent on operating voltage, I/O loading, and I/O signal frequency. It can be
estimated as:
CL ⋅ VDD22 ⋅ f
where CL is the load capacitance, VDD2 is the I/O supply voltage, and f is the frequency of output signal.
Table 9 lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical applica-
tion under specific conditions. The following conditions are assumed for all cases:
s VDD2 is 3.3 V.
s The load capacitance for each output and I/O pin is 30 pF.
For applications with values of CL, VDD2, or f that differ from those assumed for Table 9, the above formula can be
used to adjust the I/O power dissipation values in the table.
Table 9. Typical I/O Power Dissipation at 3.3 V
Internal
Peripheral
SEMI†
Pin(s)
ED[31:0]
ERWN[1:0]
EA0
EA[18:1]
ESEG[3:0]
EROMN
ERAMN
Type
I/O‡
O
O
O
O
O
O
No. of
Pins
32
2
1
18
4
1
1
Signal
Frequency
(MHz)
CLK/4
CLK/4
CLK/8
CLK/4
CLK/4
CLK/12
CLK/12
I/O Power Dissipation (mW)
185 MHz
200 MHz
242
261
15
16.2
7.6
8.1
273
294
60
65.9
5.1
5.4
5.1
5.4
EION
O
1
CLK/12
5.1
5.4
ECKO
O
1
CLK/2
30.2
32
BIO〈0—1〉 IO〈0—1〉BIT[6:0] O§
14
1
PIU
PD[15:0]
I/O‡
16
30
4.6
4.6
78.5
78.5
PINT
O
1
1
PIBF
O
1
30
POBE
O
1
30
0.33
0.33
9.8
9.8
9.8
9.8
PRDY
O
1
30
SIU〈0—1〉
SICK〈0—1〉
O
2
8
SOCK〈0—1〉
O
2
8
SOD〈0—1〉
O
2
8
SIFS〈0—1〉
O
2
0.03
SOFS〈0—1〉
O
2
0.03
9.8
5.2
5.2
5.2
0.019
0.019
9.8
5.2
5.2
5.2
0.019
0.019
† Assumptions: the SEMI is configured for a 32-bit external data bus (the ESIZE pin is high). The contribution from the EACKN pin is
negligible.
‡ Assumption: the pins switch from input to output at a 50% duty cycle.
§ Assumption: the corresponding core has configured these pins as outputs.
20
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