DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

7 Electrical Characteristics and Requirements (continued)

7.3 Power Dissipation (continued)

7.3.2 I/O Power Dissipation (continued)

Power dissipation due to the input buffers is highly dependent upon the input voltage level. At full CMOS levels,

essentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the

threshold of VDD2/2, high current can flow. See Section 7.1 for more information.

WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup.

Otherwise, high currents might flow.

7.4 Power Supply Sequencing Issues

The DSP16410B requires two supply voltages. The use of dual voltages reduces internal device power consump-

tion while supporting standard 3.3 V external interfaces. The external (I/O) power supply voltage is VDD2, the inter-

nal supply voltage is VDD1, and the internal analog supply voltage is VDD1A. VDD1 and VDD1A are typically

generated by the same power supply, with VDD1A receiving enhanced filtering near the device. In the discussion

that follows, VDD1 and VDD1A are assumed to rise and fall together, and are collectively referred to as VDD1

throughout the remainder of this section.

Power supply design is a system issue. Section 7.4.1 describes the recommended power supply sequencing spec-

ifications to avoid inducing latch-up or large currents that may reduce the long term life of the device. Section 7.4.2

discusses external power sequence protection circuits that may be used to meet the recommendations discussed

in Section 7.4.1.

7.4.1 Supply Sequencing Recommendations

Control of powerup and powerdown sequences is recommended to address the following key issues. See Figure 6

and Table 10, on page 22 for definitions of the terms VSEP, TSEPU, and TSEPD.

1. If the internal supply voltage (VDD1) exceeds the external supply voltage (VDD2) by a specified amount, large

currents may flow through on-chip ESD structures that may reduce the long term life of the device or induce

latch-up. The difference between the internal and external supply voltages is defined as VSEP. It is recom-

mended that the value of VSEP specified in Table 10 be met during device powerup and device powerdown.

External components may be required to ensure this specification is met (see Section 7.4.2).

2. During powerup, if the external supply voltage (VDD2) exceeds a specified voltage (1.2 V) and the internal sup-

ply voltage (VDD1) does not reach a specified voltage (0.6 V) within a specified time interval (TSEPU), large cur-

rents may flow through the I/O buffer transistors. This is because the I/O buffer transistors are powered by

VDD2 but their control transistors powered by VDD1 are not at valid logic levels. If the requirement for TSEPU

cannot be met, external components are recommended (see Section 7.4.2).

3. During powerdown, if the internal supply voltage (VDD1) falls below a specified voltage (0.6 V) and the external

supply voltage (VDD2) does not fall below a specified voltage (1.2 V) within a specified time interval (TSEPD),

large currents may flow through the I/O buffer transistors. This is because the control transistors (powered by

VDD1) for the I/O buffer transistors are no longer at valid logic levels while the I/O buffer transistors remain pow-

ered by VDD2. If the requirement for TSEPD cannot be met, external components are recommended (see

Section 7.4.2).

Agere Systems Inc.

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