S25FL127SABMFI003 View Datasheet(PDF) - Cypress Semiconductor
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Description
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
5.3.3
IO3 / RESET# Input Initiated Hardware (Warm) Reset
The IO3 / RESET# signal functions as a RESET# input when enabled by SR2[5]=1 and CS# is high for more than tCS time or when
Quad Mode is not enabled (CR1V[1]=0). The IO3 RESET# input provides a hardware method of resetting the flash memory device
to standby state. The IO3 / RESET# input has an internal pull-up to VCC and may be left unconnected if Quad mode is not used.
When the IO3 / RESET# feature and Quad mode are both enabled, IO3 / RESET# is ignored for tCS following CS# going high, to
avoid an unintended Reset operation. This allows some time for the memory or host system to actively drive IO3 / RESET# to a valid
level following the end of a transfer. Following the end of a Quad I/O read the memory will actively drive IO3 high before disabling
the output during tDIS. Following a transfer in which IO3 was used to transfer data to the memory, e.g. the QPP command, the host
system is responsible for driving IO3 high before disabling the host IO3 output. The integrated pull-up on IO3 will then hold IO3 until
the host system actively drives IO3 / RESET# to initiate a reset. If CS# is driven low to start a new command, IO3 / RESET# is used
as IO3.
When the device is not in quad mode or when CS# is high, and the IO3 / RESET# transitions from VIH to VIL for > tRP, the device
terminates any operation in progress, makes all outputs high impedance, ignores all read/write commands and resets the interface
to standby state. The hardware reset process requires a period of tRPH to complete. During tRPH, the device will reset register states
in the same manner as power-on reset but, does not go through the full reset process that is performed during POR. If the POR
process did not complete correctly for any reason during power-up (tPU), RESET# going low for tRP will initiate the full POR process
instead of the hardware reset process and will require tPU to complete the POR process. IO3 / RESET# must be high for tRS
following tPU or tRPH, before going low again to initiate a hardware reset.
If Quad mode is not enabled, and if CS# is low at the time IO3 / RESET# is asserted low, CS# must return high during tRPH before it
can be asserted low again after tRH.
The RESET command is independent of the state of RESET#. If IO3 / RESET# is high or unconnected, and the RESET instruction
is issued, the device will perform software reset.
Table 12. Hardware Reset Parameters
Parameter
Description
Limit
Time
Unit
tRS
Reset Setup -Prior Reset end and RESET# high before RESET#
low
Min
50
ns
tRPH
tRP
tRP
tRH
Reset Pulse Hold - RESET# low to CS# low
RESET# Pulse Width
RESET# Pulse Width (only when AutoBoot enabled)
Reset Hold - RESET# high before CS# low
Min
35
µs
Min
200
ns
Max
5
µs
Min
50
ns
Notes:
1. IO3 / RESET# Low is ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when
CS# may go Low.
2. If Quad mode is enabled, IO3 / RESET# Low is ignored during tCS.
3. Sum of tRP and tRH must be equal to or greater than tRPH.
Figure 26. Hardware Reset when Quad Mode is not enabled and IO3 / Reset# is Enabled
tRP
IO3_RESET#
Any prior reset
tRH
tRH
tRPH
tRS
tRPH
CS#
Figure 27. Hardware Reset when Quad Mode and IO3 / Reset# are Enabled
IO3_RESET#
CS#
Prior access using IO3 for data
tDIS
tCS
tRP
Reset Pulse
tRH
tRPH
Document Number: 001-98282 Rev. *I
Page 33 of 142
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