RM7065A-350T View Datasheet(PDF) - PMC-Sierra
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RM7065A-350T Datasheet PDF : 52 Pages
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RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 2 is a simplification of the pipeline section and illustrates the basics of the instruction issue
mechanism.
Figure 3 Instruction Issue Paradigm
Instruction
Cache
Dispatch
Unit
F Pipe IBus
M Pipe IBus
FP
F Pipe
FP
M Pipe
Integer
F Pipe
Integer
M Pipe
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
Table 2 Dual Issue Instruction Classes
integer
floating-
load/store point
branch
add, sub, or,
xor, shift, etc.
lw, sw, ld, sd,
ldc1, sdc1,
mov, movc,
fmov, etc.
fadd, fsub,
fmult, fmadd,
fdiv, fcmp,
fsqrt, etc.
beq, bne,
bCzT, bCzF, j,
etc.
4.3 Pipeline
The logical length of both the F and M pipelines is five stages with state committing in the register
write, or W, pipe stage. The physical length of the floating-point execution pipeline is actually
seven stages but this is completely transparent to the user.
Figure 4 shows instruction execution within the RM7065A when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation since the out-of-order completion of loads, stores, and long latency floating-point
operations can result in there being even more instructions in process than what is shown.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2010145, Issue 2
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