RM7065A-350T View Datasheet(PDF) - PMC-Sierra
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RM7065A-350T Datasheet PDF : 52 Pages
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RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 6 Kernel Mode Virtual Addressing (32-bit)
0xFFFFFFFF Kernel virtual address space
(kseg3)
0xE0000000 Mapped, 0.5GB
0xDFFFFFFF
0xC0000000
Supervisor virtual address space
(ksseg)
Mapped, 0.5GB
0xBFFFFFFF
0xA0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
0x80000000
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x7FFFFFFF
User virtual address space
(kuseg)
Mapped, 2.0GB
0x00000000
When the RM7065A is configured for 64-bit addressing, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
4.13 Joint TLB
For fast virtual-to-physical address translation, the RM7065A uses a large, fully associative TLB
that maps virtual pages to their corresponding physical addresses. As indicated by its name, the
JTLB is used for both instruction and data translations. The JTLB is organized as pairs of even/odd
entries, and maps a virtual address and address space identifier (ASID) into the large, 64 GB
physical address space. By default, the JTLB is configured as 48 pairs of even/odd entries. The
optional 64 even/odd entry configuration is set at boot time.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured, on a
per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4x multiples). The CP0
PageMask register is loaded with the desired page size of a mapping, and that size is stored into the
TLB, along with the virtual address, when a new entry is written. Thus, operating systems can
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2010145, Issue 2
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