RM7065A-350T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7065A-350T

RM7065A™ Microprocessor with On-Chip Secondary Cache

PMC-Sierra 

RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet

Preliminary

Table 5 Floating Point Latencies and Repeat Rates

Operation

Latency

single/double

Repeat Rate

single/double

fadd

4

1

fsub

4

1

fmult

4/5

1/2

fmadd

4/5

1/2

fmsub

4/5

1/2

fdiv

21/36

19/34

fsqrt

21/36

19/34

frecip

21/36

19/34

frsqrt

38/68

36/66

fcvt.s.d

4

1

fcvt.s.w

6

3

fcvt.s.l

6

3

fcvt.d.s

4

1

fcvt.d.w

4

1

fcvt.d.l

4

1

fcvt.w.s

4

1

fcvt.w.d

4

1

fcvt.l.s

4

1

fcvt.l.d

4

1

fcmp

1

1

fmov, fmovc

1

1

fabs, fneg

1

1

4.9 Floating-Point General Register File

The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the

floating-point load and store double instructions, LDC1 and SDC1, the floating-point unit can

take advantage of the 64-bit wide data cache and issue a floating-point coprocessor load or store

doubleword instruction in every cycle.

The floating-point control register file contains two registers; one for determining configuration

and revision information for the coprocessor, and one for control and status information. These

registers are primarily used for diagnostic software, exception handling, state saving and restoring,

and control of rounding modes.

To support superscalar operations the FGR has four read ports and two write ports and is fully

bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port

are used to support the combined multiply-add instruction while the fourth read and second write

port allows for concurrent floating-point load or store and conditional move operations.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

17

Document ID: PMC-2010145, Issue 2

Share Link: