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RM7065A-350T View Datasheet(PDF) - PMC-Sierra

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RM7065A-350T Datasheet PDF : 52 Pages
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RM7065AMicroprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
the core primitive of almost all signal processing algorithms. Therefore, using the RM7065A
eliminates the need for a separate DSP engine in many embedded applications.
4.7 Floating-Point Coprocessor
The RM7065A incorporates a high-performance fully pipelined floating-point coprocessor which
includes a floating-point register file and autonomous execution units for multiply/add/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the M pipe of the integer unit. The superscalar capabilities of the RM7065A
allow floating-point computation instructions to issue concurrently with integer instructions.
4.8 Floating-Point Unit
The RM7065A floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is
supported.
The RM7065A maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Floating-point operations include:
add
subtract
multiply
divide
square root
reciprocal
reciprocal square root
conditional moves
conversion between fixed-point and floating-point format
conversion between floating-point formats
floating-point compare
Table 5 gives the latencies of the floating-point instructions in internal processor cycles.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers Internal Use
16
Document ID: PMC-2010145, Issue 2

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