RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

associativity and 16 KB size results in a cache which is physically indexed and physically tagged.

Since the effective physical index eliminates the potential for virtual aliases in the cache, it is

possible that some operating system code can be simplified vis-a-vis the RM5200 Family, R5000

and R4000 class processors.

The data cache is non-blocking; that is, a miss in the data cache will not necessarily stall the

processor pipeline. As long as no instruction is encountered which is dependent on the data

reference which caused the miss, the pipeline will continue to advance. Once there are two cache

misses outstanding, the processor will stall if it encounters another load or store instruction.

A 32-byte (eight word) line size is used to maximize the communication efficiency between the

data cache and the secondary cache, tertiary cache, or memory system.

The data array portion of the data cache is 64 bits wide and protected by byte parity while the tag

array holds a 24-bit physical address, three housekeeping bits, a two bit cache state field, and has

two bits of parity protection.

The normal write policy is write-back, which means that a store to a cache line does not

immediately cause memory to be updated. This increases system performance by reducing bus

traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a

subsequent memory operation. Software can, however, select write-through on a per-page basis

when appropriate, such as for frame buffers. Cache protocols supported for the data cache are:

1. Uncached

Reads to addresses in a memory area identified as uncached will not access the cache. Writes

to such addresses will be written directly to main memory without updating the cache.

2. Write-back

Loads and instruction fetches will first search the cache, reading the next memory hierarchy

level only if the desired data is not cache resident. On data store operations, the cache is first

searched to determine if the target address is cache resident. If it is resident, the cache contents

will be updated, and the cache line marked for later write-back. If the cache lookup misses, the

target line is first brought into the cache and then the write is performed as above.

3. Write-through with write allocate

Loads and instruction fetches will first search the cache, reading from memory only if the

desired data is not cache resident; write-through data is never cached in the secondary or

tertiary caches. On data store operations, the cache is first searched to determine if the target

address is cache resident. If it is resident, the primary cache contents will be updated and main

memory will also be written leaving the write-back bit of the cache line unchanged; no writes

will occur into the secondary or tertiary. If the cache lookup misses, the target line is first

brought into the cache and then the write is performed as above.

4. Write-through without write allocate

Loads and instruction fetches will first search the cache, reading from memory only if the

desired data is not cache resident; write-through data is never cached in the secondary or

tertiary caches. On data store operations, the cache is first searched to determine if the target

address is cache resident. If it is resident, the cache contents will be updated and main memory

will also be written leaving the write-back bit of the cache line unchanged; no writes will

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

22

Document ID: PMC-2002175, Issue 1

Share Link: