RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

Figure 7 Tertiary Cache Hit and Miss

Master

SysClock

Processor

Tertiary(Hit)

Processor

Tertiary(Miss)

SysAD

TcLine[17:0]

Addr

Index

Data0 Data1 Data2 Data3

Addr

Index

Data0 Data1

TcWord[1:0]

I0

I1

I2

I3

I0

I1

I2

I3

TcTCE*

TcMatch

TcDCE*

TcCWE*

TcDOE*

System

Data0 Data1

I0

I1

Other capabilities of the tertiary interface include block write, tag invalidate, and tag probe. For

details of these transactions as well as detailed timing waveforms for all the tertiary transactions,

see the R5000 or RM7000 Bus Interface Specifications. The tertiary cache tag can easily be

implemented with standard components such as the Motorola MCM69T618.

The RM7000 cache attributes for the instruction, data, internal secondary, and optional external

tertiary caches are summarized in Table 6.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

25

Document ID: PMC-2002175, Issue 1

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