RM7000-250T View Datasheet(PDF) - PMC-Sierra

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Description

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RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

secondary entry will no longer have such an entry. Such a primary line is called an orphan. In

general, cache lines at level n+1 of the hierarchy are called parents of level n’s children.

Another RM7000 cache management optimization occurs for the case of a secondary cache line

replacement where the secondary line is dirty and has a corresponding dirty line in the primary. In

this case, since it is permissible to leave the dirty line in the primary, it is not necessary to write the

secondary line back to main memory. Taking this scenario one step further, a final optimization

occurs when the aforementioned dirty primary line is replaced by another line and must be written

back, in this case, it will be written directly to memory bypassing the secondary cache.

4.20 Secondary Caching Protocols

Unlike the primary data cache, the secondary cache supports only uncached and block write-back.

As noted earlier, cache lines managed with either of the write-through protocols will not be placed

in the secondary cache. A new caching attribute, write-back with secondary and tertiary bypass,

allows the secondary, and the tertiary if present, to be bypassed entirely. When this attribute is

selected, the secondary and tertiary will not be filled on load misses and will not be written on

dirty write-backs from the primary.

4.21 Tertiary Cache

Like the RM5270, RM5271 and R5000, the RM7000 has direct support for an external cache. In

the case of the RM527x chips this is a secondary cache whereas for the RM7000 this cache

becomes a level-3, or tertiary cache. The tertiary cache is direct mapped and block write-through

with byte parity protection for data. The RM7000 tertiary operates identical to the secondary of the

RM527x and R5000 while supporting additional size increments to 4M and 8M byte caches.

The tertiary interface uses the SysAD bus for data and tags while providing a separate bus,

TcLine, for addresses, and a handful of tertiary specific control signals (for the complete set, see

Pin Listing).

A tertiary read looks nearly identical to a standard processor read except that the tag chip enable

signal, TcTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe and

indicating to the external controller that a tertiary cache access is being performed. As a result, the

external controller monitors the tertiary hit signal, TcMatch, and if a hit is indicated the controller

will abort the memory read and will refrain from acquiring control of the system interface. Along

with TcTCE*, the processor also asserts the tag data enable signal, TcTDE*, which causes the tag

RAMs to latch the SysAD address internally for use as the replacement tag if a cache miss occurs.

On a tertiary miss, a refill is accomplished with a two signal handshake between the data output

enable signal, TcDOE*, which is deasserted by the controller and the tag and data write enable

signal, TcCWE*, which is asserted by the processor. Figure 7 illustrates a tertiary cache hit

followed by a miss.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002175, Issue 1

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