RM7000-250T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7000-250T

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet Released

PMC-Sierra 

RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet

Released

occur into the secondary or tertiary. If the cache lookup misses, then only main memory is

written.

5. Fast Packet Cache™ (Write-back with secondary and tertiary bypass)

Loads and instruction fetches first search the primary cache, reading from memory only if the

desired data is not resident; the secondary and tertiary are not searched. On data store

operations, the primary cache is first searched to determine if the target address is resident. If

it is resident, the cache contents are updated, and the cache line marked for later write-back. If

the cache lookup misses, the target line is first brought into the cache and then the write is

performed as above.

Associated with the Data Cache is the store buffer. When the RM7000 executes a STORE

instruction, this single-entry buffer gets written with the store data while the tag comparison is

performed. If the tag matches, then the data is written into the Data Cache in the next cycle that the

Data Cache is not accessed (the next non-load cycle). The store buffer allows the RM7000 to

execute a store every processor cycle and to perform back-to-back stores without penalty. In the

event of a store immediately followed by a load to the same address, a combined merge and cache

write will occur such that no penalty is incurred.

4.19 Secondary Cache

The RM7000 has an integrated 256 KB, four-way set associative, block write-back secondary

cache. The secondary has the same line size as the primaries, 32 bytes, is logically 64-bits wide

matching the system interface and primary widths, and is protected with doubleword parity. The

secondary tag array holds a 20-bit physical address, two housekeeping bits, a three bit cache state

field, and two parity bits.

By integrating a secondary cache, the RM7000 is able to dramatically decrease the latency of a

primary cache miss without dramatically increasing the number of pins and the amount of power

required by the processor. From a technology point of view, integrating a secondary cache

maximally leverages CMOS semiconductor technology by using silicon to build the structures that

are most amenable to silicon technology; silicon is being used to build very dense, low power

memory arrays rather than large power hungry I/O buffers.

Further benefits of an integrated secondary are flexibility in the cache organization and

management policies that are not practical with an external cache. Two previously mentioned

examples are the 4-way associativity and write-back cache protocol.

A third management policy for which integration affords flexibility is cache hierarchy

management. With multiple levels of cache, it is necessary to specify a policy for dealing with

cases where two cache lines at level n of the hierarchy would, if possible, be sharing an entry in

level n+1 of the hierarchy. The policy followed by the RM7000 is motivated by the desire to get

maximum cache utility and results in the RM7000 allowing entries in the primaries which do not

necessarily have a corresponding entry in the secondary; the RM7000 does not force the primaries

to be a subset of the secondary. For example, if primary cache line A is being filled and a cache

line already exists in the secondary for primary cache line B at the location where primary A’s line

would reside then that secondary entry will be replaced by an entry corresponding to primary

cache line A and no action will occur in the primary for cache line B. This operation will create the

aforementioned scenario where the primary cache line which initially had a corresponding

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

23

Document ID: PMC-2002175, Issue 1

Share Link: