ADM9240 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
ADM9240 Datasheet PDF : 22 Pages
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To accommodate fans of different speed and/or different num-
bers of output pulses per revolution, a prescaler (divisor) of 1, 2,
4 or 8 may be added before the counter. The default value is 2,
which gives a count of 153 for a fan running at 4400 rpm pro-
ducing two output pulses per revolution.
The count is calculated by the equation:
Count = (22.5 × 103 × 60) /(rpm × Divisor)
For constant speed fans, fan failure is normally considered to
have occurred when the speed drops below 70% of nominal,
which would correspond to a count of 219. Full scale (255)
would be reached if the fan speed fell to 60% of its nominal
value. For temperature controlled variable speed fans the situa-
tion will be different.
Table III shows the relationship between fan speed and time per
revolution at 60%, 70% and 100% of nominal rpm for fan
speeds of 1100 rpm, 2200 rpm, 4400 rpm and 8800 rpm, and
the divisor that would be used for each of these fans, based on
two tacho pulses per revolution.
Table III. Fan Speeds and Divisors
Divisor
1
2
4
8
Nominal
rpm
8800
4400
2200
1100
Time per
70% Rev
(ms) rpm
6.82 6160
13.64 3080
27.27 1540
54.54 770
Time per
60% Rev
(ms) rpm
9.74 5280
19.48 2640
38.96 1320
77.92 660
Time per
60% Rev
(ms)
11.36
22.73
45.45
90.9
Note that Fan 1 and Fan 2 Divisors are programmed into Bits 4
to 7 of the VID0–VID3/Fan Divisor Register.
LIMIT VALUES
Fans in general will not overspeed if run from the correct volt-
age, so the failure condition of interest is underspeed due to
electrical or mechanical failure. For this reason only low speed
limits are programmed into the limit registers for the fans. It
should be noted that, since fan period rather than speed is being
measured, a fan failure interrupt will occur when the measure-
ment exceeds the limit value.
MONITORING CYCLE TIME
The monitoring cycle time depends on the fan speed and num-
ber of tacho output pulses per revolution. Two complete periods
of the fan tacho output (three rising edges) are required for each
fan measurement. Therefore, if the start of a fan measurement
just misses a rising edge, the measurement can take almost three
tacho periods. In order to read a valid result from the fan value
registers, the total monitoring time allowed after starting the
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fan speed.
Although the fan monitoring cycle and the analog input moni-
toring cycle are started together, they are not synchronized in
any other way.
ADM9240
FAN MANUFACTURERS
Manufacturers of cooling fans with tachometer outputs are
listed below:
NMB Tech
9730 Independence Ave.
Chatsworth, California 91311
818-341-3355
818-341-8207
Model Frame Size
ACiFrMflow
2408NL 2.36 in sq. × 0.79 in (60 mm sq. × 20 mm) 9–16
2410ML 2.36 in sq. × 0.98 in (60 mm sq. × 25 mm) 14–25
3108NL 3.15 in sq. × 0.79 in (80 mm sq. × 20 mm) 25–42
3110KL 3.15 in sq. × 0.98 in (80 mm sq. × 25 mm) 25–40
Mechatronis Inc.
P.O. Box 613
Preston, WA 98050
800-453-4569
Models—Various sizes available with tach output option.
Sanyo Denki/Keymarc Electronics
468 Amapola Ave.
Torrance, CA 90501
310-783-5400
Models—109P Series
CHASSIS INTRUSION INPUT
The Chassis Intrusion (CI) input is an active high input/open-
drain output intended for detection and signalling of unautho-
rized tampering with the system. An external circuit powered
from the system’s CMOS backup battery is used to detect and
latch a chassis intrusion event, whether the system is powered up
or not. Once a chassis intrusion has been detected and latched,
the CI input will generate an interrupt when the system is pow-
ered up.
The actual detection of chassis intrusion is performed by an
external circuit that will, for example, detect when the cover has
been removed. A wide variety of techniques may be used for the
detection:
– Microswitch that opens or closes when the cover is removed.
– Reed switch operated by magnet fixed to the cover.
– Hall-effect switch operated by magnet fixed to the cover.
– Phototransistor that detects light when cover is removed.
The chassis intrusion interrupt will remain asserted until the
external detection circuit is reset. This can be achieved by set-
ting Bit 6 of the Configuration Register, or Bit 7 of the Chassis
Intrusion Clear Register to one, which will cause the CI pin to be
pulled low for at least 20 ms. These register bits are self-clearing.
REV. 0
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