ADM9240 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

ADM9240

Low Cost Microprocessor System Hardware Monitor

ON Semiconductor 

ADM9240

The structure of the NAND tree is shown in Figure 13.

Beginning with A1 and working clockwise around the chip, each

pin can be toggled and a resulting toggle can be observed on

NTEST_OUT/A0.

Allow for a typical propagation delay of 500 ns.

A1

SDA

SCL

FAN1

FAN2

VID0

VID1

VID2

VID3

VID4

NTEST_OUT

Figure 13. NAND Tree

Note: If any of the inputs shown in Figure 9 are unused, they

should not be connected directly to ground, but via a resistor

such as 10 kΩ. This will allow the ATE (Automatic Test Equip-

ment) to drive every input high so that the NAND tree test can

be properly carried out.

USING THE ADM9240

POWER-ON RESET

When power is first applied, the ADM9240 performs a “power-

on reset” on several of its registers. Registers whose power-on

values are not shown have power-on conditions that are indeter-

minate (this includes the Value and Limit Registers). The ADC

is inactive. In most applications, usually the first action after

power-on would be to write limits into the Limit Registers.

Power-on reset clears or initializes the following registers (the

initialized values are shown in Table VI:

– Configuration Register

– Serial Address Register

– Interrupt (INT) Status Registers #1 and #2

– Interrupt (INT) Mask Registers #1 and #2

– VID /Fan Divisor Register

– VID4 Register

– Chassis Intrusion Clear Register

– Temperature Configuration Register

– Test Register

– Compatibility Register

– Analog Output Register

INITIALIZATION

Configuration Register INITIALIZATION performs a similar,

but not identical, function to power-on reset. The Test Register

and Analog Output Register are not initialized.

Configuration Register INITIALIZATION is accomplished by

setting Bit 7 of the Configuration Register high. This bit auto-

matically clears after being set.

Using the Configuration Register

Control of the ADM9240 is provided through the Configuration

Register. The ADC is stopped upon power-up, and the INT_Clear

signal is asserted, clearing the INT output. The Configuration

Register is used to start and stop the ADM9240; enable or dis-

able interrupt outputs and modes, and provide the initialization

function described above.

Bit 0 of the Configuration Register controls the monitoring loop

of the ADM9240. Setting Bit 0 low stops the monitoring loop

and puts the ADM9240 into a low power mode thereby reduc-

ing power consumption. Serial bus communication is still pos-

sible with any register in the ADM9240 while in low power

mode. Setting Bit 0 high starts the monitoring loop.

Bit 1 of the Configuration Register enables or disables the INT

Interrupt output. Setting Bit 1 high enables the INT output,

setting Bit 1 low disables the output.

Bit 3 of the Configuration Register is used to clear the INT

interrupt output when set high. The ADM9240 monitoring

function will stop until Bit 3 is set low. Interrupt Status Register

contents will not be affected.

Bit 4 of the Configuration Register is used to initiate a mini-

mum 20 ms RESET signal on the RESET output if the function

is enabled by Bit 7 in Register 44.

Bit 6 of the Configuration Register is used to reset the Chassis

Intrusion (CI) output pin when set high.

Bit 7 of the Configuration Register is used to start a Configura-

tion Register Initialization when taken high.

STARTING CONVERSION

The monitoring function (analog inputs, temperature and fan

speeds) in the ADM9240 is started by writing to the Configura-

tion Register and setting Start (Bit 0), high, INT_Enable (Bit 1)

high and INT_Clear (Bit 3) low. Apart from initially starting

together, the analog measurements and fan speed measurements

proceed independently and are not synchronized in any way.

The analog measurements will be completed in no more than

353 µs. The time taken to complete the fan speed measurements

depends on the fan speed and the number of tacho output pulses

per revolution.

Once the measurements have been completed, the results can be

read from the Value Registers at any time.

Table IV shows the measurement sequence for the analog inputs.

Table IV. Measurement Sequence

Measurement # Parameter

1

2

3

4

5

6

7

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LOW POWER AND SHUTDOWN MODE

The ADM9240 can be placed in a low power mode by setting

Bit 0 of the Configuration register to 0. This disables the inter-

nal ADC. Full shutdown mode may then be achieved by setting

Bit 0 of the Test Register to 1. This turns off the analog output

and stops the monitoring cycle, if running, but it does not affect

the condition of any of the registers. The device will return to its

previous state when this bit is reset to zero.

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