DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

7 Electrical Characteristics and Requirements (continued)

7.4 Power Supply Sequencing Issues (continued)

7.4.2 External Power Sequence Protection Circuits

This section discusses external power sequence protection circuits which may be used to meet the recommenda-

tions discussed in Section 7.4.1. For the purpose of this discussion, the dual supply configuration of Figure 7 will

be used. The recommendations for this series supply system apply to parallel supply configurations where a com-

mon power bus simultaneously controls both the internal and external supplies.

SYSTEM

POWER BUS

EXTERNAL

POWER

REGULATOR

VDD2

2.4 V

D0

INTERNAL

POWER

REGULATOR

D1

DSP1640C

VDD1

Figure 7. Power Supply Example

1563.a(F)

Figure 7 illustrates a typical supply configuration. The external power regulator provides power to the internal

power regulator.

Use of schottky diode D1 to bootstrap the VDD2 supply from the VDD1 supply is recommended. D1 ensures that the

VSEP recommendation is met during device powerdown and powerup. In addition, D1 protects the DSP16410C

from damage in the event of an external power regulator failure.

Diode network D0, which may be a series of diodes or a single zener diode, bootstraps the VDD1 supply. After

VDD2 is a fixed voltage above VDD1 (2.4 V as determined by D0), the VDD2 supply will power VDD1 until D0 is cut

off as VDD1 achieves its operating voltage. If TSEPU/TSEPD recommendations are met, D0 is not required. Since D0

protects the DSP16410C from damage in the event of an internal supply failure and reduces TSEPU, use of D0 is

recommended. To ensure D0 cutoff during normal system operation, D0’s forward voltage (VF) should be 2.4 V. D0

should be selected to ensure a minimum VDD1 of 0.8 V under DSP load.

Agere Systems Inc.

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