DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

DSP16410C Digital Signal Processor

Data Addendum

May 2001

8 Timing Characteristics and Requirements (continued)

8.7 Interrupt and Trap

VOH–

ECKO† VOL–

INT‡

t21

t22

† ECKO is free-running.

‡ INT is one of INT[3:0] or TRAP.

Figure 13. Interrupt and Trap Timing Diagram

5-4018(F).g

Table 21. Timing Requirements for Interrupt and Trap

Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

Abbreviated Reference

Parameter

Min

t21

Interrupt Setup (high to low)

8

t22

INT/TRAP Assertion Time (high to low) 2T†

† T = internal clock period (CLK).

Max

—

—

Unit

ns

ns

30

Agere Systems Inc.

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