Data Addendum
May 2001
DSP16410C Digital Signal Processor
8 Timing Characteristics and Requirements (continued)
8.6 JTAG
TCK0, TCK1 VIH
VIL
TMS0, TMS1 VIH
VIL
TDI0, TDI1 VIH
VIL
VOH
TDO0, TD01
VO L
t155
t12
t13
t14
t15
t156
t16
t17
t18
t19
t20
Figure 12. JTAG I/O Timing Diagram
Table 19. Timing Requirements for JTAG I/O
Abbreviated Reference
Parameter
Min Max Unit
t12
TCK Period (high to high)
50
—
ns
t13
TCK High Time (high to low)
22.5
—
ns
t14
TCK Low Time (low to high)
22.5
—
ns
t155
TCK Rise Transition Time (low to high)
0.6
—
V/ns
t156
TCK Fall Transition Time (high to low)
0.6
—
V/ns
t15
TMS Setup Time (valid to high)
7.5
—
ns
t16
TMS Hold Time (high to invalid)
5
—
ns
t17
TDI Setup Time (valid to high)
7.5
—
ns
t18
TDI Hold Time (high to invalid)
5
—
ns
Table 20. Timing Characteristics for JTAG I/O
Abbreviated Reference
t19
t20
Parameter
TDO Delay (low to valid)
TDO Hold (low to invalid)
Min Max Unit
—
15
ns
0
—
ns
5-4017(F).d
Agere Systems Inc.
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