DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

8 Timing Characteristics and Requirements (continued)

8.1 Phase-Lock Loop

Table 12. PLL Requirements

Parameter

VCO Frequency Range

(VDD1A = 1.575 V)

Input Jitter at CKI

PLL Lock Time

CKI Frequency with PLL Enabled

CKI Frequency with PLL Disabled

fCKI/(D† + 2)

† D is the PLL input divider and is defined by pllfrq[13:9].

Symbol

fVCO

—

tL

fCKI

fCKI

—

Min

200

—

—

6

0

3

Max

500

200

0.5

40

50

20

Unit

MHz

ps-rms

ms

MHz

MHz

MHz

8.2 Wake-Up Latency

Table 13 specifies the wake-up latency for the low-power standby mode. The wake-up latency is the delay between

exiting low-power standby mode and resumption of normal execution.

Table 13. Wake-Up Latency

Condition

Low-power Standby Mode

(AWAIT (alf[15]) = 1)

PLL Disabled‡

During Standby

PLL Enabled‡

During Standby

Wake-Up Latency

(PLL Deselected† During (PLL Enabled‡ and Selected†

Normal Execution)

During Normal Execution)

3T§

3T§ + tL††

3T§

3T§

† The PLL is deselected if the PLLSEL field (pllcon[0]) is cleared, which is the default after reset. The PLL is selected if the PLLSEL field

(pllcon[0]) is set.

‡ The PLL is disabled (powered down) if the PLLEN field (pllcon[1]) is cleared, which is the default after reset. The PLL is enabled (powered

up) if the PLLEN field (pllcon[1]) is set.

§ T = CLK clock cycle (fCLK = fCKI if PLL deselected; fCLK = fCKI * ((M + 2)/((D + 2) * f(OD))) if PLL enabled and selected).

†† tL = PLL lock-in time (see Table 12).

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