DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

Data Addendum

May 2001

DSP16410C Digital Signal Processor

8 Timing Characteristics and Requirements (continued)

8.4 Reset Circuit

The DSP16410C has three external reset pins: RSTN, TRST0N, TRST1N. At initial powerup or if any supply volt-

age (VDD1, VDD1A, or VDD2) falls below VDD MIN*, a device reset is required and RSTN, TRST0N, TRST1N must

be asserted simultaneously to initialize the device.

Note: The TRST0N and TRST1N pins must be asserted even if the JTAG controller is not used by the application.

VDD1,

VDD1A

RAMP

RSTN,

TRST0N,

TRST1N

VIH

VIL

OUTPUT VOH

PINS † VOL

VDD MIN

t146

t153

t8

t10

t11

CKI

5-4010(F).r

† When both INT0 and RSTN are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a

3-state condition. With RSTN asserted and INT0 not asserted, EION, ERAMN, EROMN, EACKN, ERWN0, and ERWN1 outputs are driven

high. EA[18:0], ESEG[3:0], and ECKO are driven low.

Figure 10. Powerup and Device Reset Timing Diagram

Table 16. Timing Requirements for Powerup and Device Reset

Abbreviated Reference

Parameter

Min

t8

RSTN, TRST0N, and TRST1N Reset Pulse (low to high)

7T†

t146

VDD1, VDD1A MIN to RSTN, TRST0N, and TRST1N Low

2T†

t153

RSTN, TRST0N, and TRST1N Rise (low to high)

—

† T = internal clock period (CKI).

Max Unit

—

ns

—

ns

60

ns

Table 17. Timing Characteristics for Device Reset

Abbreviated Reference

t10

t11

Parameter

RSTN Disable Time (low to 3-state)

RSTN Enable Time (high to valid)

Min

Max

Unit

—

50

ns

—

50

ns

Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high cur-

rents may flow.

* See Table 5 on page 14.

Agere Systems Inc.

27

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