DSP16410C Digital Signal Processor
Data Addendum
May 2001
8 Timing Characteristics and Requirements (continued)
8.5 Reset Synchronization
t24
VIH–
CKI
VIL–
VIH–
RSTN VIL–
EROMN
(EXM = 1)
t126
Note: See Section 8.9 for timing characteristics of the EROMN pin.
Figure 11. Reset Synchronization Timing
FETCH OF FIRST
INSTRUCTION BEGINS
5-4011(F).i
Table 18. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference
t126
t24
† T = internal clock period (CKI).
Parameter
Reset Setup (high to high)
CKI to Enable Valid
Min
Max
3
T/2 – 1†
4T + 0.5 4T + 4
Unit
ns
ns
28
Agere Systems Inc.