DSP16410C View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP16410C

Digital Signal Processor

Agere -> LSI Corporation 

DSP16410C Digital Signal Processor

Data Addendum

May 2001

8 Timing Characteristics and Requirements (continued)

8.3 DSP Clock Generation

t1

CKI

VIH–

VIL–

t3

t2

t5

ECKO VOH–

VOL–

t4

t6

Figure 9. I/O Clock Timing Diagram

Table 14. Timing Requirements for Input Clock

Abbreviated Reference

Parameter

t1†

Clock In Period (high to high)

Min Max Unit

20 —‡ ns

t2

Clock In Low Time (low to high)

10 — ns

t3

Clock In High Time (high to low)

10 — ns

† For timing requirements shown, it is assumed that CKI (not the PLL output) is selected as internal clock source. If

the PLL is selected as the internal clock source, the minimum required CKI period is 25 ns and the maximum

required CKI period is 167 ns.

‡ Device is fully static, t1 is tested at 100 ns input clock option, and memory hold time is tested at 0.1 s.

Table 15. Timing Characteristics for Input Clock and Output Clock

Abbreviated Reference

t4

t5

t6

† T = internal clock period (CLK).

Parameter

Clock Out High Delay (low to low)

Clock Out Low Delay (high to high)

Clock Out Period (high to high)

Min Max Unit

— 10 ns

— 10 ns

T† — ns

5-4009(F).i

26

Agere Systems Inc.

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