MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MPC2605ZP66R Datasheet PDF : 30 Pages
| |||
with the fourth assertion of TA of the first cache read, so that
the data tenure for the second cache read may commence in
the next cycle.
Because it only recognizes qualified assertions of
CPU DBG, the MPC2605 must not be aware of the proces-
sor’s assertions of DBB. This means that the DBB pin of the
MPC2605 must be tied to a pullup resistor rather than con-
nected to the system DBB to which all other devices are
connected. This forces the system arbiter to a level of so-
phistication such that it only supplies qualified data bus
grants and thus the DBB signal is unnecessary to the whole
system.
Note: In a multi–chip configuration each MPC2605 device
acts as an independent cache. Zero wait state data stream-
ing can only occur if the back to back read hits occur in a giv-
en device. If the second read hit is not in the device as the
first read hit, a wait state will occur between the two data ten-
ures (2–1–1–1–2–1–1–1 timing).
Data Bus Parking
The MPC2605 has the ability to respond to a processor
read or write hit starting in the cycle after the processor has
asserted TS. This is referred to as a 2–1–1–1 response.
However, even though the MPC2605 has this ability, it is de-
pendent upon the system to allow this quick of a response to
occur. As discussed above, a data tenure cannot start until
the master has been given a qualified bus grant. In order for
the data tenure to start the cycle after TS is asserted, the
data bus must be granted in the cycle coincident with the
assertion of TS. At bus speeds of 66 MHz it is extremely diffi-
cult for an arbiter to detect an assertion of TS and itself as-
sert CPU DBG in the same cycle. In order to realistically
allow this situation to occur, CPU DBG must be asserted in-
dependent of the processor’s assertion of TS.
Data bus parking is a system feature whereby the proces-
sor always has a qualified data bus grant when the data bus
is idle. It is also a requirement for systems which seek to take
advantage of the 2–1–1–1 response time capabilities of the
MPC2605. This feature is typically present in arbiters that
have the level of sophistication necessary to support data
streaming. But it is also a feature of systems that do not even
have a data bus arbiter. In these systems the data bus grant
of every device in the system is tied to ground. The assertion
of DBB by the current data bus master effectively removes
the qualified data bus grant of all devices in the system, in-
cluding its own. Note that in systems that have no data bus
arbiter that it is impossible to take advantage of data stream-
ing.
There is another caveat associated with data bus parking.
Care must be taken when using data bus parking along with
Fast L2 mode. In normal bus mode when the processor
reads data off the bus, it will wait one cycle before passing
the data on to internal functional units. The purpose of this
one cycle waiting period is to check for an assertion of
DRTRY, which invalidates the data that has been already
read. One of the advantages of running the processor in Fast
L2 mode is that this internal processor wait state is removed.
A problem will arise, however, if the processor is given
data the cycle after TS is asserted, as is possible with the
MPC2605, and the transaction is aborted by some other de-
vice asserting ARTRY. Because the processor will not sam-
ple ARTRY until two cycles after the assertion of TS, the data
read off the bus will have already been forwarded to the
internal functional units. Thus, incorrect results may occur in
the system.
To avoid this situation in a system that seeks to run Fast L2
mode with the data bus parked, there must be a guarantee
that ARTRY will never be asserted for cache read hits. This
is a further requirement to be imposed upon the DMA bridge
and the memory controller. If this guarantee cannot be made,
the data bus cannot be parked when running in Fast L2
mode.
Processor Reads
When the processor issues a read transaction, the
MPC2605 does a tag lookup to determine if this data is in
the cache. If there is a cache hit and CI is not asserted, the
MPC2605 will assert L2 CLAIM and supply the data to the
processor when the data tenure starts.
If the processor issues a cache–inhibited read (CI as-
serted) and the MPC2605 detects a cache hit to a non–dirty,
or clean, cache line, the line will be marked invalid. If the
cache–inhibited read hits a dirty line, the MPC2605 will as-
sert ARTRY and write the dirty line back to memory.
If the read misses in the cache, the MPC2605 will perform
a linefill only if it is a burst read and it is not marked cache–in-
hibited. During a linefill, the MPC2605 stores the data pres-
ent on the bus as it is supplied by the memory controller.
Processor Writes
The conditions for asserting L2 CLAIM for processor writes
are almost the same as for processor reads. There must be a
cache hit and CI must not be asserted. In addition, however,
WT must not be asserted. Single beat writes that are marked
either write–through or cache–inhibited that hit in the cache
cause the MPC2605 to assert ARTRY and write the dirty line
back to memory.
Transaction Pipelining
As explained in Pipeline Depth, the MPC2605 can only
handle one level of pipelining on the bus. Since the assertion
of L2 CLAIM gives it the ability to assert AACK, the
MPC2605 has the ability to control this pipeline depth for
transactions that are cache hits by delaying its assertion of
AACK.
Pipelined cache hits are transactions that hit in the cache
but occur while there is still an outstanding data transaction
on the bus. The timing of the assertion of AACK for a pipe-
lined cache hit is dependent upon the completion of the pre-
vious transaction. For explanation purposes, the previous
transaction will be referred to as transaction one. The pipe-
lined cache hit will be referred to as transaction two.
If transaction one is a cache hit, the MPC2605 will be the
slave device for the transaction. Since, for burst operations,
the MPC2605 always asserts TA for four consecutive clock
cycles, the end of the data tenure for transaction one will be
at a deterministic clock cycle. In this case, AACK for transac-
tion two can be asserted coincident with the last assertion of
TA for transaction one. If transaction one is not a cache hit,
the MPC2605 will wait until after the data tenure for transac-
tion one has completed before asserting AACK to complete
the address tenure of transaction two.
MPC2605
12
MOTOROLA
Share Link: 