MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale
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MPC2605ZP66R Datasheet PDF : 30 Pages
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The MPC2605 treats multiple processors as one proces-
sor. Thus, the same restrictions on pipelining depth are true
with regard to how many processor transactions can be out-
standing at any one time. There can only be one data
transaction from ANY processor pipelined on top of a current
data transaction that was issued by ANY processor.
The data tenures for all processors must be performed in
the same order as the address tenures on a system–wide
basis. If processor one makes a request and then processor
two makes a request, processor one’s data tenure must pre-
cede processor two’s data tenure. Note that this is not a 60X
bus restriction, but rather a restriction necessary for proper
operation of the MPC2605.
The MPC2605 keeps coherent with the L1 caches of multi-
ple processors as defined by the MESI (modified–exclusive–
shared–invalid) protocol without actually implementing the
protocol. This is possible for two reasons. Since the
MPC2605 is a look–aside cache, all transactions are moni-
tored by all devices on the bus. Also, the MPC2605 cannot,
on its own, modify data. Thus, if one processor requests ex-
clusive access to a cache line, it is not necessary for the
MPC2605 to invalidate its copy of the data, as would be re-
quired under the MESI protocol. If a second processor re-
quests the same data, the transaction will cause the first
processor to assert ARTRY. This will prevent the MPC2605
from supplying stale data to the second processor.
As discussed in Data Bus Parking, care must be taken
when parking the data bus in Fast L2 mode. By the nature of
MP systems running under the MESI protocol there will be
assertions of ARTRY to abort cache read hits. Thus, in an
MP system, the data bus cannot be parked to any processor
if the system is to be run in Fast L2 mode.
PWRDN
An assertion of PWRDN will cause the MPC2605 to go into
a low–power sleep state. This state is entered after PWRDN
is synchronized and both the address and data buses are
idle. All data is retained while in the sleep state.
The behavior of the MPC2605 upon negation of PWRDN
is dependent upon the state of WT at the rising edge of
HRESET. If WT is asserted at reset, the MPC2605 will
invalidate all cache entries when PWRDN is negated. If WT
is negated at reset, the MPC2605 will leave all cache entries
as they were prior to the assertion of PWRDN. However, in
this situation, the system designer must insure that no bus
activity occur within two microseconds of the negation of
PWRDN.
Note: While in the sleep state the MPC2605 does not dis-
able its internal clock network. The low power state current
stated in this specification assumes that the system clock is
not toggling.
ASYNCHRONOUS SIGNALS
The MPC2605 supports four asynchronous control sig-
nals. These signals were originally defined in the PowerPC
reference platform (PReP) specification. Because these sig-
nals are defined to be asynchronous, the MPC2605 must
synchronize them internally. This process takes eight clock
cycles. Thus, to guarantee recognition by the MPC2605,
assertions of any one of these signals must last a minimum
of eight clock cycles.
L2 FLUSH
When L2 FLUSH is asserted, the MPC2605 initiates an in-
ternal sequence that steps through every cache line present.
Valid lines that are clean are immediately marked invalid.
Valid lines that are dirty must be written back to main
memory.
To keep memory up to date, the MPC2605 must still moni-
tor all transactions on the bus. Any transaction that is not a
processor burst write will cause the MPC2605 to assert
ARTRY. Burst writes cause the MPC2605 to do a lookup on
the affected address and mark the line invalid if it is present.
Because the MPC2605 must still monitor all transactions,
it cannot use the tag RAM for the flush sequence unless
there is a guarantee that no new transaction will be initiated
on the bus. The only way to ensure that no new transactions
will occur is for the MPC2605 to be granted the bus. Thus,
upon entering the sequence initiated by the assertion of
L2 FLUSH, the MPC2605 will assert L2 BR. As soon as
L2 BG is asserted, the MPC2605 can start stepping through
the tag RAM entries.
L2 FLUSH need not be held asserted for the flush se-
quence to complete. Once started the sequence will run to
completion unless overridden by an assertion of HRESET.
L2 MISS INH
When L2 MISS INH is asserted, the MPC2605 will not load
any new data into the cache. The data already present will
remain valid and the MPC2605 will respond to cache hits.
This condition only lasts as long as L2 MISS INH is asserted.
When L2 MISS INH is negated, the MPC2605 will start to
bring new data into the cache when there are cache misses.
L2 TAG CLR
When L2 TAG CLR is asserted, the MPC2605 will invali-
date all entries in the cache. This internal sequence is the
same as the one initiated by an assertion of HRESET. During
this sequence, the MPC2605 will not participate in any bus
transaction. However, it will keep track of all bus transactions
so that when the sequence is finished, the MPC2605 can im-
mediately participate in the next bus transaction.
As is the case with assertions of L2 FLUSH, an assertion
of L2 TAG CLR need not be held for the duration of the se-
quence. Once asserted the sequence will run to completion
regardless of the state of L2 TAG CLR.
L2 UPDATE INH
When L2 UPDATE INH is asserted, the MPC2605 is
disabled from responding to cacheable transactions. Bus
transactions continue to be monitored so that as soon as
L2 UPDATE INH is negated, the MPC204GA can participate
in the next transaction.
MPC2605
14
MOTOROLA
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