MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2605ZP66R

Integrated Secondary Cache for PowerPC Microprocessors

Motorola => Freescale 

READ/WRITE MISS

Figure 6 is an illustration of a processor read or write miss

that causes the MPC2605 to replace a dirty line. L2 BR is

asserted two clocks after TS. The dirty data to be replaced is

moved into the internal cast out buffer (COB) at the same

time the new data is written into the cache. Note that the

copyback operation occurs after the processor request is

satisfied. In addition, no delay is added to the processor

transaction. It proceeds as fast as the memory controller will

allow.

1

2

3

4

5

6

7

8

9

10

11

12

CLK

CPU BG

L2 BR

L2 BG

TS

A0 – A31

A

B

TBST

L2 CLAIM

AACK

CPU DBG

L2 DBG

DBB

TA

DH0 – DH31,

DL0 – DL31

A1

A2

A3

A4

B1

B2

B3

B4

LEGEND

Signal driven to the MPC2605

Signal driven by the MPC2605

High–Z

Figure 6. Read or Write Miss Followed by Castout

MPC2605

20

MOTOROLA

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