MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2605ZP66R

Integrated Secondary Cache for PowerPC Microprocessors

Motorola => Freescale 

MULTIPLE READ/WRITE HITS (NORMAL BUS MODE)

Figure 2 is an illustration of MPC2605 pipeline depth limit

with multiple read hits. The MPC2605 supports only one

level of address pipelining for data transfer. Therefore, it

must hold off on its assertion of AACK for a pipelined TS until

the data tenure for the first TS is done. The MPC2605

asserts AACK at the same time as the fourth TA for data

tenures that it controls.

CLK

CPU BG

TS

A0 – A31

TBST

L2 CLAIM

1

2

3

4

5

6

7

8

9

10

11

A

B

C

AACK

CPU DBG

DBB

TA

DH0 – DH31,

DL0 – DL31

A1

A2

A3

A4

B1

B2

B3

B4

LEGEND

Signal driven to the MPC2605

Signal driven by the MPC2605

High–Z

Figure 2. Multiple Burst Read (or Write) Hits

MPC2605

16

MOTOROLA

Share Link: