MPC2605ZP66R View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MPC2605ZP66R

Integrated Secondary Cache for PowerPC Microprocessors

Motorola => Freescale 

MULTIPLE READ HITS (FAST L2 MODE)

Back to back pipelined burst read hits for the MPC604 in

Fast L2 mode, also called data streaming mode, are shown

in Figure 4. Note that CPU DBG is negated except for the

cycles coincident with the fourth TA of each data tenure. This

is a requirement for data streaming. Note also that DBB is

not shown. For proper operation in Fast L2 mode the DBB

pin of the MPC2605 must be tied to a pull–up resistor.

CLK

CPU BG

TS

A0 – A31

TBST

L2 CLAIM

AACK

CPU DBG

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

TA

DH0 – DH31,

DL0 – DL31

A1

A2

A3

A4

B1

B2

B3

B4

C1

C2

C3

LEGEND

Signal driven to the MPC2605

Signal driven by the MPC2605

High–Z

Figure 4. Multiple Burst Read Hits in Fast L2 Mode

MPC2605

18

MOTOROLA

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